Technical Field
The present invention relates generally to the field of processors, and in particular to branch instruction decoding.
Description of the Related Art
Modern processors may take advantage of certain combinations of instructions by fusing two instructions together to form a single operation. More particularly, when a flow control instruction such as a conditional branch instruction follows a compare instruction, for example, the two instructions can be fused to form a single micro-op. This is sometimes referred to as branch fusion. The branch instruction may use the condition code register or processor status register to determine whether or not to cause a program control flow to change (i.e., branch to be taken). The status flags may be modified as a result of execution of a compare instruction, for example. Branch fusion may provide improvements in processing. For example, one benefit may be that the fused micro-op may execute in one execution cycle rather than two. However, in instruction set architectures that include special branch instructions that do not make use of the architectural registers such as the condition code or status registers to decide whether or not to take the branch, a normal branch fusion may not be performed.